With increasing demand for compact and high-performance electronic equipment in these years, the sizes of semiconductor chips and circuit boards are becoming smaller and smaller, and the number of terminals and the number of layers are increasing. Packaging densities of electronic components on a circuit board are also increasing. The increase in the number of terminals and reduction in a pitch between terminals cause another demand for miniaturization of rewiring interconnects used in circuit boards or packages. For this reason, micro-fabrication techniques for rewiring interconnects are attracting attention.
Many types of circuit boards, including a package substrate, wafer-level package (WLP) and silicon interposer, are known. In a structure in which multiple chips are connected via a silicon interposer to a package substrate, the line width of rewiring interconnects (i.e., chip-to-chip interconnects) in the silicon interposer is becoming smaller. As for a fabrication technique, a damascene process is replacing a conventional semi-additive process.
In general, rewiring interconnects for built-up (sub-composite) substrates used in a package substrate or rewiring interconnects in a wafer-level package are fabricated by a semi-additive process. However, it is difficult for a semi-additive process to control the etching line width and the adhesion strength of a copper (Cu) seed layer and a titanium (Ti) glue layer (or barrier metal layer).
Accordingly, a damascene process is preferred when fabricating fine interconnect patterns with the line width and the space width equal to or less than 5 μm.
FIG. 1A illustrates a damascene process, where a trench is formed in an insulation film 101 and a layer stack of a titanium film and a copper film (Cu/Ti stack) is formed in the trench by sputtering. Ti serves as a barrier metal 103 and Cu serves as a plating seed metal. The trench is filled with an electrolytic copper plating layer 104. Surplus copper is removed by chemical mechanical polishing (CMP). Then, the barrier metal 103 remaining on the surface of the substrate 101 is removed by CMP or wet etching to provide a damascene interconnect. (See, for example, Patent Documents 1 and 2 listed below).
A metal cap 106 is generally provided as a cap barrier layer over the surface of the damascene interconnect using cobalt (Co), nickel (Ni) or the like because the post-CMP surface of the interconnect is exposed without a barrier. Then, an insulation film 102 is formed over the substrate 101.
If the metal cap 106 is formed by electroless plating, the material of the metal cap 106 is not deposited over the barrier metal 103 formed of titanium or the like. For this reason, the boundary “A” between the Cu layer 104, the barrier metal 103, and the metal cap 106 is feeble. Due to diffusion of copper from the boundary, the reliability and durability of products are degraded.